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INTEGRATED CIRCUITS
DATA SHEET
TDA8753A YUV 8-bit analog-to-digital interface
Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Jan 12
Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
FEATURES * Triple analog-to-digital converter * 8-bit resolution * Sampling rate up to 20 MHz * Power dissipation of 500 mW (typical) * Internal clamp functions * 4 : 1 : 1 output data encoder * Y binary output * U, V two's complement outputs * Sample rate converter permits programmable horizontal compression factors from 1 to 2 * Serial microcontroller interface * TTL compatible inputs. QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD INL DLE SNR fclk Ptot Notes PARAMETER analog supply voltage digital supply voltage analog supply current digital supply current integral non-linearity differential non-linearity signal-to-noise ratio without harmonics maximum conversion rate total power dissipation note 2 fclk = 16 MHz; ramp input fclk = 16 MHz; ramp input; Y fclk = 16 MHz; ramp input; U and V note 1 CONDITIONS MIN. 4.75 4.75 - - - - - 43 20 - TYP. 5.0 5.0 55 45 0.75 0.5 0.6 - - 500 APPLICATIONS
TDA8753A
* High-speed analog-to-digital conversion for video signal digitizing in 4 : 1 : 1 format * 100 Hz improved definition TV for all formats (4/3, 16/9, 14/9 etc.). GENERAL DESCRIPTION The TDA8753A is a monolithic CMOS 8-bit video low-power analog-to-digital conversion interface for YUV signals. It converts the YUV analog input signal into 8-bit binary coded digital words in format 4 : 1 : 1 at a sampling rate of 20 MHz. All analog signal inputs are clamped. The device includes a digital sample rate converter for variable compression with a factor 1 to 2.
MAX. 5.25 5.25 63 55 - 0.75 0.9 - - 650
UNIT V V mA mA LSB LSB LSB dB MHz mW
1. The signal-to-noise ratio without harmonics is measured using a 16 MHz clock frequency. This value is given for a 4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels). 2. The external resistor (between VDDA and Iref) fixing internal static currents influences Ptot. The value of the resistor should be 5.6 k (5%). ORDERING INFORMATION TYPE NUMBER TDA8753A PACKAGE NAME SDIP42 DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) VERSION SOT270-1
1996 Jan 12
2
Product specification
TDA8753A
Fig.1 Block diagram.
handbook, full pagewidth
1996 Jan 12
CLK 16 9 10 V DDD2 V SSD2 DIFF 8 BIT ADC DELAY 18 PREFILTER LOW-PASS FILTER MIXER Y0 Y7 DELAY SIGN DELTA ON/OFF
Iref CLAMP
BLOCK DIAGRAM
V DDA1
27 37
20
CLAMP CIRCUIT
Philips Semiconductors
VSSA1
39
INY
38
x 1.5
VDDA2
34
CLAMP CIRCUIT
VSSA2 8 BIT ADC INTERPOLATION DOWNSAMPLING CORING AND PREFILTER
36
YUV 8-bit analog-to-digital interface
INU
35
x 1.5
VDDA3
31
ON/OFF NOTCH
HOLD
DELTA
RESET
CLAMP CIRCUIT
U AND V FORMATTER
12/14 11/13
UV0 UV1
3
8 BIT ADC INTERPOLATION DOWNSAMPLING CORING AND PREFILTER ON/OFF NOTCH DELAY ON/OFF NOTCH DELTA HOLD DELTA RESET ENABLE SIGN HOLD SERIAL INTERFACE 15 25 41 UPDA 40 VDDD1 VSSD1 24 V SSD3 42 DTO RESET 22 21 23 V50 MODE0 MSCAN MODE1 UPCL 19 H ref
VSSA3
33
INV
32
x 1.5
PHI
Vref(H)
29
TDA8753A
DECref(L)
28
MEMORY INTERFACE 18 WEI
WEO DELAY 17
26
30
VSSA5
VSSA4
MBE424
Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
PINNING SYMBOL Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 VDDD2 VSSD2 U1 U0 V1 V0 VSSD3 CLK WEO WEI Href CLAMP MODE1 MODE0 MSCAN VSSD1 VDDD1 VSSA5 Iref DECref(L) Vref(H) VSSA4 VDDA3 INV VSSA3 VDDA2 INU VSSA2 VDDA1 INY VSSA1 1996 Jan 12 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DESCRIPTION Y data output, bit 7 (MSB) Y data output, bit 6 Y data output, bit 5 Y data output, bit 4 Y data output, bit 3 Y data output, bit 2 Y data output, bit 1 Y data output, bit 0 (LSB) digital supply voltage 2, (+5 V) digital ground 2 U data output, bit 1 (n) U data output, bit 0 (n - 1) V data output, bit 1 (n) V data output, bit 0 (n - 1) digital ground 3 clock input write enable output write enable input horizontal reference signal input clamp control input test mode select test mode select test pin digital ground 1 digital supply voltage 1 (+5 V) analog ground 5 current level reference decoupling output from reference LOW reference voltage input (HIGH) analog ground 4 analog supply voltage 3, (+5 V) V analog voltage input analog ground 3 analog supply voltage 2 (+5 V) U analog voltage input analog ground 2 analog supply voltage 1 (+5 V) Y analog voltage input analog ground 1 4
V1 13 V0 14 VSSD3 15 CLK 16 WEO 17 WEI 18 Href 19 CLAMP 20 MODE1 21
MBE425
TDA8753A
SYMBOL UPCL UPDA V50
PIN 40 41 42
DESCRIPTION control clock input serial interface data input data execution input
handbook, halfpage
Y7 1 Y6 2 Y5 3 Y4 4 Y3 5 Y2 6 Y1 7 Y0 8 VDDD2 9 VSSD2 10
42 V50 41 UPDA 40 UPCL 39 VSSA1 38 INY 37 VDDA1 36 VSSA2 35 INU 34 VDDA2 33 VSSA3
U1 11 TDA8753A 32 INV U0 12 31 VDDA3 30 VSSA4 29 Vref(H) 28 DEC ref(L) 27 I ref 26 VSSA5 25 VDDD1 24 VSSD1 23 MSCAN 22 MODE0
Fig.2 Pin configuration.
Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
FUNCTIONAL DESCRIPTION Analog-to-digital converter The TDA8753 implements 3 independent CMOS 8-bit analog-to-digital converters. The converters use a multi-step approach with offset compensated comparators. Clamping An internal clamping circuit is provided in each of the 3 analog channels. The analog pins INY, INV and INU are switched to on-chip clamping levels during an active pulse on the clamp input CLP.The clamping level in the Y channel is code level 16. The clamping level in the U/V channel is code level 128 (output code 0 in the 2's complement description) see Tables 3 and 4. Sample rate converter A sample rate converter is integrated in the TDA8753A to facilitate programming of the horizontal aspect ratio which can be varied from a factor 1 to 2. This includes conversion from 16/9 to 14/9 and 4/3. In the U/V channel a linear interpolation is sufficient because of the four times oversampling. Discrete time oscillator (DTO) A discrete time oscillator is used to calculate for every sample of the phase delay that is needed for a given compression factor. Serial interface (SIO) All controls are sent to the TDA8753A via a serial microprocessor interface. Data from this interface will be made active at the vertical input pulse V50.
TDA8753A
The TDA8753A has three addressable control registers which can be loaded via the signals UPDA and UPCL. The format of this bus is fixed according to mode 0 of the 8051 family UART at 1 Mbaud (8 bits are transmitted, LSB first). Serial interface protocol POWER-ON STATE When powered up the SIO is in an unknown state and all data in the registers is random. When signals are applied to UPCL and UPDA in this state, the behaviour is unpredictable. The only way to exit from this state to a known state is apply a V50 signal to the TDA8753A. INITIALIZATION STATE From power-on or any other state, the INIT state is entered (at the latest) one TDA8753A clock period after the end of the V50 HIGH state. In this state the F0, F1 and F2 TDA8753A registers are loaded with the values that are in the corresponding line buffers BF0, BF1 and BF2. The first time V50 is issued after power-on, this data is unknown. After a rising UPCL edge has been detected, the address reception state is entered. ADDRESS RECEPTION STATE Bits are counted at each rising UPCL edge. The next 8 bits received on UPDA line are considered as address bits. The address reception is illustrated in Fig.3.
handbook, halfpage
incoming stream
1
1
1
1
0
0
1
0
first data bit of data value for address F2 register last address bit received (in this example address received is F2 hex)
first bit received
MBE426
Fig.3 Address reception.
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
The TDA8753A registers have address F0, F1 and F2 hexadecimal notation. Whenever the received address (decoded on the first 8 bits received) is one of these, the event is recorded in such a way that the next data received by the TDA8753A will be captured in the line buffer BF0, BF1 and BF2 respectively. When 8 bits have been received, the data reception state is entered. The address reception state can also be exited at any time when V50 goes HIGH. The F0, F1 and F2 registers may not be loaded properly if there is some activity in progress on the incoming line. DATA RECEPTION STATE
TDA8753A
The next 8 bits are considered as data bits according to the format of Fig.4. When 8 data bits have been received, the data is recorded in the BF0, BF1 or BF2 line buffers if the previous address recorded was F0 hex, F1 hex or F2 hex respectively. The bit count is then reset to zero and the address reception state is entered. This state may be ended any time when V50 goes HIGH but in that condition F0, F1 and F2 registers may not be loaded properly.
handbook, halfpage
incoming stream
last address bit received
1
1
0
X
X
X
X
X
first bit of next address stream
first data bit of value (e.g. for address F2 register) 0:2 = 110(DEL 0:2 )
MBE427
Data value is F2
Fig.4 Data reception.
Table 1
Data allocation PARAMETER CF UV_CORING UV_FILTER_TYPE PRE_ON NOTCH_ON DTO_ON SEL_DTO_RES WEO_DEL_SEL FUNCTION compression factor value will be (1 + cf/255) which results in a range from 1 to 2 coring definition in U and V channels; see Table 5 notch filter selection in U and V channels (0 = 4 MHz; 1 = 2 MHz) luminance prefilter active notch prefilter active DTO control select DTO reset (0 = WE; 1 = Href) select delay in WEO luminance delay compression (see Table 5) not used; load 0 5 7:2 NUMBER OF BITS 8 2 1 1 1 1 1 BIT POSITION 7:0 1:0 2 3 4 5 6
ADDRESS F0H F1H
F2H
Y_VAR_DELAY
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA VDDA - VDDD VI Vclk(p-p) Tstg Tamb PARAMETER digital supply voltage analog supply voltage supply voltage difference input voltage AC input voltage for switching (peak-to-peak value) storage temperature operating ambient temperature referenced to AGND referenced to DGND CONDITIONS MIN. -0.3 -0.3 -0.5 - - -55 0
TDA8753A
MAX. 6.5 6.5 +0.5 VDDA VDDD +150 +70 V V V V V
UNIT
C C
THERMAL RESISTANCE SYMBOL Rth j-a HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. CHARACTERISTICS VDDA = VDDD = 4.75 to 5.25 V; VSSA and VSSD shorted together; VDDA - VDDD = -0.1 to +0.1 V (see note 1); Vref(H) = 2.38 V; fclk = 20 MHz with 50% duty cycle; 5.6 k (5%) connected between Iref and VDDA; CL = 15 pF; Tamb = 0 to 70 C; typical values measured at VDDA = VDDD = 5 V; unless otherwise specified. SYMBOL Supply VDDA VDDD IDDA IDDD analog supply voltage digital supply voltage analog supply current digital supply current 4.75 4.75 - - 5.0 5.0 55 45 - - 7 - 5.25 5.25 63 55 V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PARAMETER thermal resistance from junction to ambient in free air VALUE 45 UNIT K/W
Digital inputs and clock input (WE, Href, CLAMP, MODE1, MODE0, SCCL, UPCL, UPDA and V50) VIL VIH CI ILI LOW level input voltage HIGH level input voltage input capacitance input leakage current 0 2.0 - VI = 0 V; VDDD = 5 V -10 0.8 VDDD 15 +10 V V pF A
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clamp and references [Iref, DECref(L) and Vref(H)] ACL Cclamp ZADC Vref(H) VDECref(L) clamping accuracy serial clamp capacitor internal impedance between pin 29 and VSSA converter reference HIGH, applied to pin 29 converter reference voltage LOW, applied to pin 28 Vref(H) = 2.38 V Y U and V -4 -1 10 - - - - - 22 420 2.38 0.39 +1 +1 - - - - LSB LSB nF V V
Y analog input (INY); Vref(H) = 2.38 V, Vref(L) = 0.39 V; see Table 4 Vi(p-p) Ii CI input voltage, full range (peak-to-peak value) input current input capacitance ramp input clamp non-active - - - - - - - 1.26 5 - - 100 15 - 100 15 -50 V nA pF
U,V analog inputs (INU and INV); Vref(H) = 2.38 V, Vref(L) = 0.39 V; see Table 4 Vi(p-p) Ii CI Inputs isolation act crosstalk between INY, INU and INV - dB input voltage (peak-to-peak value) ramp input input current input capacitance clamp non-active 1.26 5 - V nA pF
Digital outputs (Y0 to Y7, U1, U0, V1 and V0); see Table 3 VOL VOH LOW level output voltage HIGH level output voltage IOL = 1.6 mA IOH = 0.4 mA 0 2.4 - - - - - - - - 41 42 - - 0.5 VDDD - - - - - - - 0.75 0.9 - - V V
Analog signal processing (fCLK = 20 MHz) Gdiff diff fall SVR B differential gain differential phase harmonics (full scale) all components supply voltage ripple rejection bandwidth note 2 note 2 note 3; Y U and V note 4 -1 dB; note 5 1.5 1.0 -53 -55 2 6 0.75 0.5 0.6 44.5 46 % deg dB dB %/V MHz
Transfer function (fclk = 16 MHz) INL DNL SNR integral non-linearity differential non-linearity signal-to-noise ratio without harmonics ramp input ramp input; Y note 6; Y U and V LSB LSB LSB dB dB
ramp input; U and V -
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (fclk = 20 MHz; CL = 15 pF); see Figs 7 and 10; note 7 fclk tCP(H) tCP(L) tds thd td tCLKr tCLKf tsu;Href thd;Href tr tf tCLP tsu;WE thd;WE tXLXL tQVXH tXHQH tW tVC Y FUV Yfr UVfr Ystep UVstep maximum input clock frequency clock pulse width HIGH clock pulse width LOW sampling delay output hold time output delay time clock rise time clock fall time HREF set-up time HREF hold time data output rise time data output fall time minimum time for active clamp pulse width WE set-up time WE hold time serial port clock cycle time output data set-up to rising edge of clock output data hold time after rising edge of clock V50 pulse duration V50 to clock time fxtal = 12 MHz 20 22 22 - 7 - 3 3 7 3 - - 2.3 7 3 1 700 50 2 2 - - - - - - - - - 4 - - 5 5 - - 10 10 2.5 - - - - - - - 1 4 0.5 0.5 1 4 - - - - - 32 - - - - - - - - - - - - - - - - - - - - MHz ns ns ns ns ns ns ns ns ns ns ns s ns ns s ns ns ms ms
Sample rate converter (fclk = 20 MHz) Y phase accuracy UV phase accuracy Y frequency response UV frequency response Y step size UV step size fiY = 0 to 5 MHz fiUV = 0 to 1.5 MHz fiY = 0 to 5 MHz fiUV = 0 to 1.5 MHz ns ns dB dB ns ns
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
Notes to the Characteristics 1. VDDA and VDDD should be supplied from the same power supply and decoupled separately.
TDA8753A
2. Measurement carried out using video amplifier type VM700A, where the video analog signal (Y channel) is reconstructed via the DAC. 3. The input conditions are related as follows: Y - Vi(p-p) = 1.26 V, fi = 4.43 MHz U and V - Vi(p-p) = 1.26 V, fi = 1.5 MHz. 4. Supply voltage ripple rejection: SVR; relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V. SVR = [ (VI(0) - VI(255)]/[VI(o) - VI(255)]/VDDA. 5. The -1 dB bandwidth is the frequency value for which the analog reconstructed (glitch-free) output signal is compressed in term of number of codes, by -1 dB (respectively for -3 dB bandwidth). 6. The signal-to-noise ratio without harmonics is measured under a 16 MHz clock frequency. This value is given for a 4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels). 7. Output data acquisition: Output data is available after the maximum delay of td. Table 2 Mode selection MODE1 0 Table 3 Output data coding BIT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U V U1 U0 V1 V0 Y0 7 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 OUTPUT DATA Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 MODE0 0 MODE normal configuration
OUTPUT PORT Y
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
Table 4 Internal ADC data coding as a function of the analog input INPUT VOLTAGE <0.26 0.26 .... 0.34 .... 0.89 .... - 1.52 >1.52 INTERNAL BINARY OUTPUTS 00000000 00000000 00000001 ........ 00010000 ........ 10000000 ........ 11111110 11111111 11111111 VDECref(L) /1.5
TDA8753A
STEP Underflow 0 1 .... 16 .... 128 .... 254 255 Overflow Table 5
REMARKS
clamp level of Y channel clamp level of U and V channels
Vref(H) - 0.1 V/1.5
Coring and luminance delay INTERNAL CORING CORRECTION IN U AND V CHANNELS (AROUND CODE 128 LEVEL) coring off +1/-1 +1/-0 +2/-1 Y_VAR_DELAY F2:1 0 0 1 1 F2:0 0 1 0 1 INTERNAL DELAY FOR Y PATH AT PREFILTER INPUT (CLOCK PULSE) 0 1 2 3
UV_CORING F1:1 0 0 1 1 F1:0 0 1 0 1
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
1/1 page = 296 mm (Datasheet)
t CPH CLK
t CPL
27 mm
1.4 V
sample N
sample N + 1
sample N + 2
Vl
t dS DATA D0 - D7 DATA N-D DATA N-D+1 td
t HD 2.4 V DATA N-D+2 DATA N-D+2
MSB269
1.4 V 0.4 V
The value D is equal to 15.
Fig.5 Timing diagram.
TIMING
handbook, full pagewidthdigital
output level
MSA645
255
black-level clamping Y : 16 U,V : 128 0 time CLP t CLP
Fig.6 Clamp control timing.
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
handbook, full pagewidth
CLK
1
2
3
15
WE t su data
MBE430
output data valid
t hd
The output data is valid 15 clock periods after WE goes HIGH.
Fig.7 Set-up and hold time definition; WE signal.
handbook, full pagewidth
K x 15 x periods CLK
WE t su data
MBE431
output data valid
When the WE period is a whole multiple of 15 clock periods, the output data is valid without any clock delay. The internal circuit always gives an internal 15 clock period as illustrated in Fig.7.
Fig.8 Timing diagram; WE signal.
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
handbook, full pagewidth
td V50
t XLXL UPCL t XHQX
t QVXH
MBE432
Fig.9 Timing of the asynchronous interface.
handbook, full pagewidth
CLK t hd WEO YUV outputs
MBE428
Fig.10 Outputs hold time.
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
TDA8753A
handbook, full pagewidth
CLK t su;X t hd;X
MBE429
Fig.11 Digital inputs WE and HREF; set-up and hold time.
INTERNAL PIN CONFIGURATION
handbook, full pagewidth DIGITAL
INPUTS
VDDD
DIGITAL OUTPUTS
VDDD
16, 18 to 23, 40 to 42
1 to 8, 11 to 14, 17
VSSD
VSSD
ANALOG INPUTS
VDDA I 27 29 32, 35, 38 30 I VSSA VSSA VSSA
MBE419
I
Fig.12 Internal pin configuration.
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
APPLICATION INFORMATION
TDA8753A
5V 1 2 3 5V 4 5 6 5.6 H 7 8 9 10 100 nF 11 12 13 4.7 F 14 15 16 17 18 19 20 21 36 35 34 33 22 nF V 22 nF U 42 41 40 39 38 37 22 nF Y 5.6 H 4.7 F
100 nF
TDA8753A
32 31 30 29 22 nF 28 27
220 5V 220 F 220
5.6 k 26 25 24 23 22 100 nF
MBE433
220 uF
22 nF
Analog and digital supplies should be separated and decoupled. Test pins MODE1, MODE0 and MSCAN must be connected to digital ground.
Fig.13 Application diagram.
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
PACKAGE OUTLINE SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
TDA8753A
SOT270-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 42 22
pin 1 index E
1
21
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-02-13 95-02-04
1996 Jan 12
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8753A
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Product specification
YUV 8-bit analog-to-digital interface
NOTES
TDA8753A
1996 Jan 12
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040)23 53 60, Fax. (040)23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/02/pp20 Document order number: Date of release: 1996 Jan 12 9397 750 00564

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